A typical random access memory (RAM) includes an array of rows and columns of memory cells. A row of memory cells is accessed by activating a word line. The memory cells in each column are connected by Bit and inverted bit (Bit B) lines to a sense amplifier. During a read access of the memory, the sense amplifier determines the state of the memory cell having an active word line. The memory may include a sense amplifier for each memory cell along a word line. In another configuration, two or more sets of Bit and Bit B lines may be multiplexed to a sense amplifier.
One of the key parameters of a RAM is its access time. The access time for a memory cell is the sum of several components, including the time to activate the word line, the time to transfer the signal from the memory cell to the Bit and Bit B lines and the time to sense the Bit and Bit B lines with the sense amplifier. In a typical 4 megabit, 100 MHz RAM, the voltage change on an active Bit line is typically about 100 millivolts, and the potential develops on the Bit and Bit B lines at a rate of about 30 millivolts per nanosecond. Thus, approximately 3 nanoseconds, which represents 30% of the access time, are required to develop 100 millivolts on the Bit and Bit B lines. Sense amplifiers typically are configured as differential amplifiers which may have an offset error on the order of 10-20 millivolts. Since the bit line potential must overcome the offset error in order to switch the sense amplifier, the access time is increased for one of the states of the memory cell. The remainder of the access time is dominated by row decoder and word line activation, both of which are typically reduced by using lower resistance interconnect, metal strapping and/or by segmentation of the chip.
A high speed DRAM wherein bit lines are precharged to one half the supply voltage for faster sensing is disclosed by P. Gillingham et al. in IEEE Journal of Solid State Circuits, Vol. 26 No. 8, August 1991, pp. 1171-1175. A DRAM configuration wherein sense amplifier offset is stored on the bit lines is described by T. Sugibayashi et al in ISSCC95 Digest of Technical Papers, Feb. 17, 1995, pps. 254 and 255.